06 Contact
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Transmission.
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02 About
A quiet practice
in signals, silicon,
and small margins.
My engineering journey is a steady descent down the technology stack. I started out exploring web and mobile app development before diving deeper into the physical world through embedded systems and custom PCB design. Today, my core focus is VLSI. Having built everything from user interfaces to bare-metal firmware, I now spend my time at the absolute bottom of the stack, writing the SystemVerilog that dictates how silicon itself behaves.
Education
B.Tech. Instrumentation & Control Engineering
Netaji Subhas University of Technology (NSUT)
03 Toolbox
The hardware & software stack.
04 Experience & Honours
* This is a curated preview. View logbook for the full record.
05 Selected work
A short shelf of things that were carefully made.
This is a 5-stage pipelined 32-bit RISC-V processor (RV32I) built in Verilog
This is a single-cycle 32-bit RISC-V processor (RV32I) built in SystemVerilog, to get hands-on experience with computer architecture, datapath routing, and RTL.
Wrote an FSM to convert simple Read/Write commands into standard I2C conditions. Used tri-state logic (inout ports) to correctly control the bidirectional open-drain SDA line.
Built a parameterized SPI Master (Mode 0) supporting continuous back-to-back data transfers with automated CS pulsing and a synchronous reset state to handle interrupted transfers.
Developed a UART transmitter and receiver module in Verilog incorporating parity checking for error detection. Built a custom baud-rate generator and verified logic via GTKWave.
